1. Field of the Invention
This invention relates to word resetting in memories and more particularly to invalidating addresses in cache memories that correspond to the address of a newly written word in the main memory of a digital computer.
2. DESCRIPTION OF THE PRIOR ART
Currently, word invalidation may be achieved by using static random access memories (SRAM) to store and alter a bit indicating whether the word at a particular address is valid. A disadvantage to such a system is that additional SRAM must be added, taking up space and also requiring additional expense.
Another system writes a word of zeros into the pertinent addresses in the auxiliary memories. The disadvantage of this system is that the address register for performing this function is tied up and also the writing mode wastes time.
In today's technology of miniaturization, the extra circuitry and increase in bar size (semiconductor material) necessary to achieve a single word reset in large SRAM-based designs is formidable if normal reset circuitry is employed.
This invention achieves single word reset without significant increase in circuitry.